The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), such as, for example, junction field-effect transistors (JFETs) and metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A JFET is a type of transistor in which the current flow through a channel of the device between a drain electrode and a source electrode is controlled by the voltage applied to a gate electrode. An MOS transistor includes a gate electrode as a control electrode that is formed overlying a semiconductor substrate and spaced-apart source and drain regions that are formed within the semiconductor substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductor substrate between the source and drain regions and beneath the gate electrode. Usually both P-channel FETs (PMOS transistors) and N-channel FETs (NMOS transistors) are used to form ICs.
FET transistors, in contrast to bipolar transistors, are majority carrier devices. For example, the gain of an MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility of the majority carriers in the transistor channel. The current-carrying capability of an MOS transistor is proportional to the mobility of the majority carriers in the channel. The mobility of electrons, the majority carrier in an NMOS transistor, can be increased by applying a longitudinal tensile stress to the channel. The tensile stress caused by the differential contraction can thus improve the performance of an NMOS transistor. Similarly, the mobility of holes, the majority carrier in a PMOS transistor, can be increased by applying a longitudinal compressive stress to the channel, thus improving the performance of the PMOS transistor.
Various methods have been used to apply stress layers to FET structures, although such methods often suffer from significant drawbacks. For example, conductive contacts to the source/drain regions often are formed through a stress layer that has been applied to the top or front side of the transistors, that is, overlying the gate electrodes. However, this interruption of the stress layer by a conductive contact compromises the integrity of the stress layer, thus decreasing the stress it applies to the channel regions. In addition, methods that form the stress layer on the backside of the transistors, that is, underlying the semiconductor substrate on and within which the transistors have been formed, typically do so early in the transistor fabrication, such as after impurity doping of source/drain regions. Thus, the stress layer is subjected to subsequent thermal processing of the transistor structure, which also can jeopardize the integrity of the stress layer. Further, if the stress layer is formed on the backside of the FET structure early in the FET structure fabrication, the stress layer often is removed when the structure is thinned for packaging and assembly. Thus, the final structure cannot benefit from the presence of the stress layer when the structure is in operation.
Accordingly, it is desirable to provide methods for fabricating a semiconductor structure having a backside stress layer that is formed after fabrication of a semiconductor device and before packaging and assembly. In addition, it is desirable to provide methods for fabricating a semiconductor structure having a backside stress layer that is formed after thermal processing steps. It also is desirable to provide methods for fabricating a semiconductor structure having backside stress layers that are not removed from the structure before packaging and assembly. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.